Compensated delay locked loop timing vernier
US5684421A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1995 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Oct 13, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timing vernier produces a set of timing signals of similar frequency and evenly distributed in phase by passing an input reference clock signal through a succession of delay stages, each stage providing a similar signal delay. A separate one of the timing signals is produced at the output of each delay stage. The reference clock signal and timing signal output of the last delay stage are supplied as inputs to a phase lock controller through separate adjustable first and second delay circuits. The phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock. In accordance with the invention, the delays of the first and second delay circuits are adjusted to compensate for controller phase lock error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.