Semiconductor memory with test circuit
US5684809A · kind A · utility
19Cited by
5References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1997 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Feb 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit and method for a semiconductor memory array such as a dynamic random access memory (DRAM) or static random access memory (SRAM) array that reduces the required testing time. A row of memory cells is concurrently written to a logic level, then read. Any faulty memory cells will discharge both true and complementary data lines through a diode or a diode-connected FET. The resulting voltage on the data line is less than its precharged high logic level, allowing detection of any faulty memory cell in the row of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.