Segmented non-volatile memory array with multiple sources having improved source line decode circuitry
US5687117A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1996 |
| Grant date | Nov 11, 1997 |
| Priority date | — |
| Expiry date | Feb 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.