OP amp circuit with variable resistance and memory system including same
US5694366A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1996 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | May 1, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G1/0088
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operational amplifier-based voltage multiplier circuit ("op amp circuit") implemented as an integrated circuit, and a memory chip including such an op amp circuit. The op amp circuit includes a variable operational feedback or input resistance (or a variable operational feedback resistance and a variable input resistance), and preferably also circuitry for controlling at least one variable resistance in response to control bits to cause the op amp circuit to assert a selected output voltage in response to a given input voltage. Preferably, each set of control bits determines a binary control word whose binary value has a simple functional relation to the value of the output voltage selected thereby. Preferably, the memory chip includes an array of memory cells (e.g, flash memory cells) and a control unit for controlling memory operations including programming, reading, and erasing the memory cells. The op amp circuit outputs each selected output voltage in response to a different binary control word asserted by the control unit. Each binary control word is preferably determined by a set of control bits whose binary value has a simple functional relation to the value of the outpu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.