System for prioritizing quiesce requests and recovering from a quiescent state in a multiprocessing system with a milli-mode operation
US5694617A · kind A · utility
27Cited by
14References
3Claims
0Family size
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Key dates
| Filing date | Mar 31, 1995 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | Mar 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A milli-mode routine handles a quiesce interrupt, and causes all the processors in the system to enter a quiesced state. A single bit of a millicode control register indicates a quiesced state and drives an output of the processor to indicate the processor is in a quiesced state. The processor receives a signal indicating all processors in the system are in a quiesced state and latches this value. The output of this latch is sent to the processor instruction unit for use as a millicode branch condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.