Semiconductor device including vertical MOSFET structure with suppressed parasitic diode operation
US5696396A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1996 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Oct 21, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A vertical MOSFET, which can control AC current flowing through a device only by the gate voltage, is obtained. On an n.sup.+ silicon layer is formed an n.sup.- silicon layer. Within the n.sup.- silicon layer is formed a p-body region. Within the p-body region is formed an n.sup.+ source region. On top of a substrate are formed a source electrode in contact only with the source region and a base electrode in contact only with the p-body region. The source electrode and the base electrode are connected to each other through a resistance at the outside. On a channel region is formed a gate electrode through a gate oxide film (insulating film). When the above semiconductor device is in the reverse bias conduction, the exciting current is controlled only by the gate voltage by setting the current flowing from a source terminal through the resistance to the base electrode, the p-body region and the n.sup.- silicon layer to be negligibly small as compared with the current flowing from the source terminal through the source electrode to the n.sup.+ source region, the channel region and the n.sup.- silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.