Method of operating a random access memory device having a plurality of pairs of memory cells as the memory device
US5699293A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1996 |
| Grant date | Dec 16, 1997 |
| Priority date | — |
| Expiry date | Oct 9, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnetic random access memory device (10) has a plurality of pairs of memory cells (21a,21b), a column decoder (31), a row decoder (32), and a comparator (60). The pair of memory cells (21a,21b) is designated by column decoder (31) and row decoder (32) in response to a memory address. Complementary bits ("0" and "1") are stored in the pair of memory cells (21a,21b). When the state in the pair of memory cell (21a,21b) is read, both bits in the pair of memory cells (21a,21b) are compared to produce an output at one read cycle time to a bit line (70). This memory device omits a conventional auto-zeroing step so that a high speed MRAM device can be attained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.