Method and apparatus for fault testing a pipelined processor
US5699506A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1995 |
| Grant date | Dec 16, 1997 |
| Priority date | — |
| Expiry date | May 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for fault testing a pipelined processor. In test mode, the stage registers are reconfigured as multiple input shift registers by switching in a few exclusive-OR gates. Also, the execute stage is prevented from executing any instructions. A unique sequential test sequence of instructions are run through the processor at normal speed. It is known that a particular test sequence (and thus a unique sequential input pattern to the MISR, assuming no faults) will result in a unique signature pattern existing in the MISR at the end of the sequence. If the signature pattern is not found in the MISR at the end of the test sequence, then it is known that a fault exists on the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.