Method for screening non-volatile memory and programmable logic devices
US5700698A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1995 |
| Grant date | Dec 23, 1997 |
| Priority date | — |
| Expiry date | Jul 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved method for screening a non-volatile memory device or programmable logic device including the steps of initially programming and then erasing a device for a predetermined number of cycles thereby providing a stressed device. Next, the stressed device is erased, providing an erased device. A first voltage value is measured across the floating gate of each cell of the erased device which is then stored for a predetermined period of time at a first predetermined temperature, providing a stored device. Next, the stored device is baked at a second predetermined temperature resulting in a baked device. Then, a second voltage value is measured across the floating gate of each cell of the baked device. Each of the first and the second voltage values are subtracted to provide a plurality of measured voltage drop values each of which are compared to an acceptable predetermined voltage drop value. The baked device is identified as defective and is discarded if any of the measured voltage drop values are greater than the acceptable predetermined voltage drop value. The first predetermined temperature is room temperature (i.e., 0.degree.-50.degree. C.), and the second predetermined t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.