Semiconductor integrated circuit device
US5700705A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Dec 23, 1997 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
Abstract
The manufacture of a memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. The manufacture of each load MISFET consists of forming source, drain and channel regions within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film, such as a polycrystalline film, than that of the drive MISFETs. The manufacture of the memory cell having such a stacked arrangement, facilitates the patterning of the source (drain) region and gate electrode of each load MISFET thereof to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type or of n-type and p-type polycrystalline silicon films, respectively, and electrical connections are formed between the drain regions of the first and second p-channel load MISFETs with that of the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.