Sealed stacked arrangement of semiconductor devices
US5701031A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1994 |
| Grant date | Dec 23, 1997 |
| Priority date | — |
| Expiry date | Jul 25, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.