Antifuse structure and method for manufacturing it
US5705849A · kind A · utility
36Cited by
20References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1996 |
| Grant date | Jan 6, 1998 |
| Priority date | — |
| Expiry date | Oct 18, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved antifuse design has been achieved by providing a structure comprising pair of alternating layers of silicon nitride and amorphous silicon sandwiched between two dual damascene connectors. Said structure provides the advantage, over the prior art, that all electrically active surfaces of the fuse structure are planar, so no potential failure spots resulting from surface unevenness can be formed. A process for manufacturing said fuse structure is also provided and involves fewer masking steps than related structures of the prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.