Cache coherent computer system that minimizes invalidation and copyback operations
US5706463A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 1997 |
| Grant date | Jan 6, 1998 |
| Priority date | — |
| Expiry date | May 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor computer system is disclosed that reduces the occurrences of invalidate and copyback operations through a memory interconnect by disabling a first write optimization of a cache coherency protocol for data that is not likely to be written by a requesting processor. Such data include read-only code segments. The code segments, including instructions and data, are shared among the multiple processors. The requesting processor generates a Read to Share Always request upon a cache miss of a read-only datablock, and generates a Read to Share request otherwise. The Read to Share Always request results in the datablock stored in cache memory being labeled as in a "shared" state, while the Read to Share request results in the datablock being labeled as in an "exclusive" state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.