Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device
US5708601A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1996 |
| Grant date | Jan 13, 1998 |
| Priority date | — |
| Expiry date | Feb 16, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus identifies redundancy memory cells that are selected to replace defective memory cells of a memory matrix that communicates with a data bus. A redundancy address register is associated with one of the redundancy memory cells. The redundancy address register stores a default state until it is programmed with an address of one of the defective memory cells. A control circuit generates a test signal during an identification mode. A detect circuit is coupled to the control circuit and to the redundancy address register and generates a default-detect signal in response to the test signal when the redundancy address register contains the default state. A data-bus multiplexer that is coupled to the redundancy-cell selection circuit, the data bus, and the control circuit couples the default detect signal to the data bus in response to the test signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.