Pipelined distributed bus arbitration system
US5710891A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1995 |
| Grant date | Jan 20, 1998 |
| Priority date | — |
| Expiry date | Mar 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/374
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e., the bus master driving the system bus, preferentially. Each arbitration task is completed within a system clock cycle regardless of processor speed. As a result, the arbitrati…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.