Second-layer phase change memory array on top of a logic device
US5714768A · kind A · utility
296Cited by
1References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1995 |
| Grant date | Feb 3, 1998 |
| Priority date | — |
| Expiry date | Oct 24, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a computational unit comprising a logic processing device, and a memory array deposited on top of and communicating with the logic processing device. More specifically, the present invention is a computational unit comprising a logic processing device, and electrically erasable phase change memory deposited on top of and communicating with the logic processing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.