Method of making a packaged semiconductor die including heat sink with locking feature
US5722161A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 1, 1996 |
| Grant date | Mar 3, 1998 |
| Priority date | — |
| Expiry date | May 1, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor die includes a heat sink having a locking feature that interlocks with the encapsulant encapsulating the die to minimize or eliminate delamination of the encapsulant from the heat sink. A surface of the heat sink can be exposed to the exterior of the encapsulant. The invention applies broadly to packaged integrated circuits including multichip modules and hybrid circuits, as well as to packaged transistors. In one embodiment of the invention, a locking moat has a cross-sectional shape that has, at a first distance beneath a locking surface of the heat sink, a width that is larger than a width at a second distance beneath the locking surface, the second distance being smaller than the first distance. The locking moat can have, for example, a "keyhole" cross-sectional shape or a circular cross-sectional shape. The locking moat can be formed by, for example, stamping or chemical etching. In another embodiment of the invention, the locking feature is a locking region. The locking region can be, for example, a plurality of dimples or deep holes formed by, for instance, stamping, grinding, mechanical or laser drilling, or chemical etching, a roughened area formed…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.