Chip carrier having an organic photopatternable material and a metal substrate
US5724232A · kind A · utility
34Cited by
13References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 1996 |
| Grant date | Mar 3, 1998 |
| Priority date | — |
| Expiry date | May 21, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.