Method of manufacturing a semiconductor device having a buried insulated gate
US5726088A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1996 |
| Grant date | Mar 10, 1998 |
| Priority date | — |
| Expiry date | Nov 15, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
In a vertical power MOSFET having a U-shaped trench gate and a method of manufacturing the same, a P-type base layer and an N.sup.+ -type emitter layer are formed on the surface of an N-type semiconductor substrate. A plurality of trenches are formed to such a depth as to reach the semiconductor substrate. After that, an oxide film and a nitride film are formed in this order on the surface of the resultant element and on the inner surfaces of the trenches. In this case, the oxide film and nitride film are each formed to have a thickness corresponding to the operating characteristics of the element at the stage of design. The nitride film of a gate wiring region is selectively removed to form an oxide film on the surface of the element. Consequently, a thick gate insulation film of the oxide films can be formed between the corner portions of the N.sup.+ -type emitter layer and a gate electrode wiring layer of the gate wiring region which is to be formed afterward, and the gate-to-source breakdown voltage can be enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.