Hot carrier injection test structure and technique for statistical evaluation
US5726458A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 1997 |
| Grant date | Mar 10, 1998 |
| Priority date | — |
| Expiry date | Feb 28, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01074
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved transistor design and methods of construction and testing for same. The novel transistor design method includes the steps of providing a transistor with multiple common gate areas; connecting each gate area to a pad; and adjusting the ratio of the area of the pad to the total of the gate areas to provide a predetermined ratio. The ratio may be adjusted by adjusting the size of the gate, in a single gate implementation, or adjusting the number of gates in a multiple gate configuration. The novel transistor includes a substrate, at least one source disposed on the substrate; at least one drain disposed on the substrate; and at least one gate disposed on the substrate between the source and the drain. The gate has a first layer of at least partially conductive material of area A.sub.g connected to a pad of area A.sub.p. In accordance with the present teachings, the antenna ratio R of the area of the pad A.sub.p to the area of the gate A.sub.g is a predetermined number. In practice, the ratio R would be chosen to be a minimum so that deleterious plasma currents attracted to the gate area would be reduced. In a particular implementation, the transistor includes plural gates …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.