Multilayer amorphous silicon antifuse
US5726484A · kind A · utility
37Cited by
10References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1996 |
| Grant date | Mar 10, 1998 |
| Priority date | — |
| Expiry date | Mar 6, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.