One transistor ferroelectric memory cell and method of making the same
US5731608A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 7, 1997 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Mar 7, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of forming a semi-conductor structure forming, on a prepared substrate, a ferroelectric memory (FEM) gate unit. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on a FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer, and which is formed on a conductive channel precursor. The structure of the semiconductor includes a substrate, which may be either bulk silicon or SOI-type silicon, conductive channels of first and second type formed above the substrate, an FEM gate unit formed above a channel region, wherein the FEM gate unit includes a lower metal layer, an FE layer, and an upper metal layer, and wherein a conductive channel of a second type is formed under the FEM gate unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.