Semiconductor integrated circuit device including a DRAM in which a cell selection transistor has a stabilized threshold voltage
US5732009A · kind A · utility
22Cited by
5References
11Claims
0Family size
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Key dates
| Filing date | Jul 22, 1996 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Jul 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/30
Abstract
A DRAM has memory cells provided at crossing points between word line conductors and bit line conductors. Each memory cell has a cell selection transistor and an information storage capacitor arranged over the bit line conductors. Unit active regions are defined in a main surface of a semiconductor substrate by a field isolation pattern. The field isolation pattern has a controlled length of extension of bird's beaks so that channel formation regions in each unit active region has almost no stepped portion to provide the cell selection transistors with a stabilized threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.