Ball grid array by partitioned lamination process
US5735452A · kind A · utility
25Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1996 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Jun 17, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0557
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
A method for forming a ball grid array to provide a chip carrier with I/O capabilities is described. The method includes combining three distinct steps into one: partitioning a solder sheet into identical solder pieces using a mask provided with openings that match the footprint of the chip carrier; reflowing the solder pieces into solder balls; and joining the balls to the I/O pads of the chip carrier. By combining these three steps into one, a high throughput, high volume, defect free and contamination free operation for forming I/O connections thus results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.