Method of making a damascene metallization
US5736457A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 5, 1997 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Mar 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1036
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor process and structure is provided for use in single or dual damascene metallization processes. A thin metal layer which serves as an etch stop and masking layer is deposited upon a first dielectric layer. Then, a second dielectric layer is deposited upon the thin metallization masking layer. The thin metallization masking layer provides an etch stop to form the bottom of the in-laid conductor grooves. In a dual damascene process, the thin metallization masking layer leaves open the via regions. Thus, the conductor grooves above the metallization masking layer and the via regions may be etched in the first and second dielectrics in one step. In a single damascene process, the thin metallization etch masking layer may cover the via regions. The etch stop and masking layer can be formed from any conductive or non-conductive materials whose chemical, mechanical, thermal and electrical properties are compatible with the process and circuit performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.