System for reordering of instructions before placement into cache to reduce dispatch latency
US5742784A · kind A · utility
8Cited by
10References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1995 |
| Grant date | Apr 21, 1998 |
| Priority date | — |
| Expiry date | Jan 25, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for reducing the dispatch latency of instructions of a processor provides for reordering the instructions in a predetermined format before the instructions enter the cache. The method and system also stores information in the cache relating to the reordering of the instructions. The reordered instructions are then provided to the appropriate execution units based upon the predetermined format. With this system, a dispatch buffer is not required when sending the instructions to the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.