Method of manufacturing copper interconnect with top barrier layer
US5744376A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1996 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Apr 8, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer ,while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.