Process of making a storage capacitor for dram memory cell

US5744388A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventor

• Anchor Chen · Pingtung City, TW

Key dates

• Filing date: Jun 11, 1996
• Grant date: Apr 28, 1998
• Expiry date: Jun 11, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

A storage capacitor structural configuration for memory cell units of DRAM devices and a process for constructing the capacitor. The capacitor includes a first electrode and a second electrode that are each electrically conducting layers, and a storage dielectric that is a dielectric layer sandwiched between the two electrodes. The silicon substrate of the device has formed thereon a field oxide layer and a transistor including a gate and a pair of source/drain regions. A first dielectric layer covers the transistor and includes a contact opening over one of the source/drain regions. The first electrode includes a first electrically conducting layer formed inside the contact opening and covering the revealed surface of the source/drain region and the first dielectric layer. A second electrically conducting layer having a rugged surface is formed on the surface of the first electrically conducting layer. A number of deep grooves are formed in the second and first electrically conducting layers, forming a grid-like configuration. The storage dielectric includes a second dielectric layer covering the surface of the grid-like configuration of the second and first electrically conductin…