Method and system for soft programming algorithm
US5745410A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1996 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Mar 21, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.