Floating point processing unit with forced arithmetic results
US5748516A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1995 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Sep 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49957
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Logic for selectively forcing arithmetic results allows a floating point unit to bypass the normal flow through arithmetic units and pipelines depending on the particular floating point operation and operand conditions. Certain forced results (e.g., forced zeros, infinities, and those corresponding to certain invalid operand conditions) may bypass arithmetic units or pipelines and rounding circuitry entirely. On the other hand, other operand dependent results (e.g., the result of X+0 and results of operations involving a NaN operand or operands) may only partially bypass the normal flow. By providing logic for selectively forcing results, arithmetic pipelines may be freed for subsequent instructions in the instruction stream. Logic for selectively forcing arithmetic results may be particularly attractive in a superscalar processor. In a superscalar processor which includes a floating point unit with forced arithmetic results, microcode to handle special cases, pipeline bypass, and early result generation can be avoided because architectural approaches for handling out-of-order results allow dependencies to be resolved irrespective of result reordering. Therefore, the early and out-…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.