Michael D. Goddard
26Patents
17h-index
12Co-inventors
78Inventor score
Filing activity: Mar 21, 1990 → Apr 4, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5632023A | Superscalar microprocessor including flag operand renaming and forwarding apparatus | Physics | 101 | Expired |
| US5689672A | Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions | Physics | 87 | Expired |
| US5574928A | Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments | Physics | 83 | Expired |
| US5649225A | Resynchronization of a superscalar processor | Physics | 74 | Expired |
| US5696955A | Floating point stack and exchange instruction | Physics | 71 | Expired |
| US5748516A | Floating point processing unit with forced arithmetic results | Physics | 69 | Expired |
| US5796974A | Microcode patching apparatus and method | Physics | 68 | Expired |
| US5796973A | Method and apparatus for decoding one or more complex instructions into concurrently dispatched simple instructions | Physics | 58 | Expired |
| US5559975A | Program counter update mechanism | Physics | 51 | Expired |
| US5237700A | Exception handling processor for handling first and second level exceptions with reduced exception latency | Physics | 27 | Expired |
| US5764938A | Resynchronization of a superscalar processor | Physics | 27 | Expired |
| US5761105A | Reservation station including addressable constant store for a floating point processing unit | Physics | 25 | Expired |
| US5903772A | Plural operand buses of intermediate widths coupling to narrower width integer and wider width floating point superscalar processing core | Physics | 22 | Expired |
| US5857089A | Floating point stack and exchange instruction | Physics | 22 | Expired |
| US6351801B1 | Program counter update mechanism | Physics | 21 | Expired |
| US5630082A | Apparatus and method for instruction queue scanning | Physics | 21 | Expired |
| US5805853A | Superscalar microprocessor including flag operand renaming and forwarding apparatus | Physics | 20 | Expired |
| US5970235A | Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions | Physics | 16 | Expired |
| US5878266A | Reservation station for a floating point processing unit | Electricity | 13 | Expired |
| US5799162A | Program counter update mechanism | Physics | 11 | Expired |
| US5896518A | Instruction queue scanning using opcode identification | Physics | 10 | Expired |
| US6035386A | Program counter update mechanism | Physics | 9 | Expired |
| US6122721A | Reservation station for a floating point processing unit | Electricity | 9 | Expired |
| US6189087A | Superscalar instruction decoder including an instruction queue | Physics | 7 | Expired |
| US5502414A | Circuit for delaying data latching from a precharged bus and method | Emerging Cross-Sectional Technologies | 5 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.