Method for minimizing the hot carrier effect in N-MOSFET devices
US5750435A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 1997 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | Jul 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/683
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An N-Channel Metal Oxide Semiconductor Field Effect Transistor (N-MOSFET) with minimum susceptibility to the Hot Carrier Effect (HCE) and a method by which the N-MOSFET is fabricated. Formed upon a semiconductor substrate is a N-MOSFET structure including a gate oxide upon a semiconductor substrate, a gate electrode upon the gate oxide and a pair of N+ source/drain regions adjoining the gate electrode and the gate oxide. Implanted into the gate oxide regions beneath the gate electrode edges is a dose of a hardening ion. The hardening ion may be either nitrogen ion or fluorine ion. The hardening ion is implanted at an angle non-orthogonal to the plane of the semiconductor substrate through means of a large tilt angle ion implant process. Optionally, a Lightly Doped Drain (LDD) source/drain electrode structure or Double Doped Drain (DDD) source/drain electrode structure may be incorporated into the N-MOSFET structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.