Programmable non-volatile memory cell and method of forming a non-volatile memory cell

US5751039A · kind A · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Ralph Kauffman · Boise, US
• Roger Lee · Boise, US

Key dates

• Filing date: Sep 19, 1997
• Grant date: May 12, 1998
• Expiry date: Sep 19, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A method of forming a non-volatile memory array includes, a) providing first and second floating gate word lines atop a semiconductor substrate, the first and second word lines being adjacent one another and defining transistor active area therebetween, the first and second word lines having inwardly opposing and facing active area sidewall edges, the first and second word lines each comprising respective nitride capping layers having a thickness of at least about 1000 Angstroms; b) providing a nitride spacer layer over the nitride capping layer; c) anisotropically etching the nitride spacer layer to produce insulating sidewall spacers over the first and second word line active area sidewall edges, the anisotropic etching leaving at least a portion of the nitride capping layer covering each of the first and second word lines, the portion of each nitride capping layer joining with one of the sidewall spacers to cover the first and second word line active area sidewall edges and thereby defining a widened mask misalignment area than were such capping layer portions not present; d) providing an oxide layer over the sidewall spacers and capping layer; e) patterning and etching the oxid…