Method of screening hot temperature erase rejects at room temperature
US5751633A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 1996 |
| Grant date | May 12, 1998 |
| Priority date | — |
| Expiry date | May 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor manufacturing process for manufacturing memory devices a method of screening hot temperature erase rejects in memory devices during wafer sort at room temperature that would be rejected at class test at high temperature. Selected cells of the memory device are subjected to a first sequence of erasure pulses at a high voltage until the selected cells are verified erased or until a first maximum number of erasure pulses has been reached, recording the number of pulses required to erase the selected cells, reading and repairing any defective memory cells, and subjecting all cells to a second sequence of erasure pulses until all cells are verified erased or until a maximum number of pulses has been reached wherein the second maximum number is a multiple of the recorded number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.