Low power CMOS array for a PLD with program and erase using controlled avalanche injection
US5754471A · kind A · utility
19Cited by
16References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low power CMOS array cell for use in a PLD device is disclosed. The cell utilizes controlled avalanche injection at the p-n junction of a transistor in the CMOS cell for programming and erasing, resulting in lower voltages than with Fowler-Nordheim tunneling and lower currents than channel hot carrier injection during program and erase. A depletion transistor having a gate connected to its source has a source-drain path supplying current to the CMOS cell to limit current required during avalanche injection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.