High density ferroelectric memory with increased channel modulation and double word ferroelectric memory cell for constructing the same
US5757042A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1996 |
| Grant date | May 26, 1998 |
| Priority date | — |
| Expiry date | Jun 14, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/701
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory based on a ferroelectric FET, the ferroelectric FET includes a gate electrode, a layer of ferroelectric material, layer of semiconducting material, a source electrode and a drain electrode. The layer of ferroelectric material is sandwiched between the gate electrode and the layer of semiconducting material, the source and drain electrodes being in contact with the layer of semiconducting material and spaced apart from one another. The memory includes a circuit for setting the ferroelectric FET to one of two states. The first state is set by applying a first voltage to the source and drain electrodes and a second voltage to the gate electrode. The second state is set by applying a third voltage to the gate and drain electrodes and fourth voltage to the source electrode. This arrangement reduces the number of pass transistors needed per ferroelectric FET to one plus a simple pulsing circuit that must be included with each word of memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.