V.sub.pp only scalable EEPROM memory cell having transistors with thin tunnel gate oxide
US5761116A · kind A · utility
28Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Oct 7, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An enhanced, scalable EEPROM memory cell is provided with a structure having a plurality of half-height tunnel oxide depletion mode transistors. The structure further has individual wordlines controlling the write and read transistors, respectively. With such a structure, lower voltages are used to program/erase the memory cell. The memory cell is scalable to small dimensions through the use of transistors having half-height tunnel oxide regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.