Method and apparatus to determine erroneous value in memory cells using data compression
US5761213A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Feb 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit are provided to detect if any bit stored in a given location in a memory is different from the data expected. The circuit includes logic to read each of the bits stored in the cells at given locations from memory and to generate a fail signal based on the data expected to be stored if the stored data is different from the expected data. The circuit also preferably includes logic to compare the True data and expect data read from each cell and generating the fail signal if they are the same. Additional logic circuitry is also preferably provided which determines if a node of the circuit remains in a precharged condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.