Write cache for servicing write requests within a predetermined address range
US5761709A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 5, 1995 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Jun 5, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system has a level 1 cache and a write cache connected to a processor, wherein the write cache has a memory address range and wherein the processor initiates a write to the write cache which is detected by the write cache. The write cache responds to the write request by storing information into the write cache if the write cache is not already full. If there is no storage location available in the write cache, a message is sent to the level 1 cache notifying that cache of this condition. The write cache responds to requests from the processor to write information stored in particular areas of the write cache into a main memory by placing that information on a external bus to be read by the main memory. The write cache then frees up those storage locations within the write cache to be used for storing subsequent writes requested by the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.