Integrated circuit device with isolated circuit elements
US5767561A · kind A · utility
65Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 1997 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | May 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/762
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device with at least one noise-sensitive element, at least one noise-generating element, and a porous silicon barrier in the substrate is disclosed. The porous silicon barrier isolates the noise-sensitive element from the signals coupled into the substrate by the noise-generating element. A process for making this device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.