Method for manufacturing a vertical transistor having a trench gate
US5770514A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1997 |
| Grant date | Jun 23, 1998 |
| Priority date | — |
| Expiry date | Jan 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
In a vertical field effect transistor having a trench gate and a method of manufacturing the same according to the present invention, p-type base and n.sup.+ -type source diffusion layers are formed in this order in a surface region of an n.sup.31 -type epitaxial layer on an n.sup.+ -type semiconductor substrate. A trench is then provided to such a depth as to penetrate the diffusion layers. A dope polysilicon layer is deposited and buried into the trench with a gate insulation film interposed between them. The polysilicon layer is etched to have the same level as that of the entrance of the trench, and a dope polysilicon layer 18 is selectively grown thereon, thereby forming a trench gate in which an upper corner portion of the trench is not covered with a gate electrode. Consequently, the concentration of electric fields at the corner portion can be mitigated thereby to increase an absolute withstand voltage of the gate and the variations in threshold voltage can be suppressed in a BT test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.