Method and circuit for transferring data with dynamic parity generation and checking scheme in multi-port DRAM
US5778007A · kind A · utility
28Cited by
6References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 11, 1997 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Mar 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described for transferring ATM data between the SAMs and the DRAM. The transfer circuits and methods include helper flip/flops to latch ATM data for editing prior to storage in the DRAM. Editing of ATM data transferred from the DRAM is also described. Dynamic parity generation and checking is described to detect errors induced during switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.