Electrically programmable interconnect structure having a PECVD amorphous silicon element

US5780919A · kind A · utility

Assignee

• QuickLogic Corporation · US

Inventors

• Hua-Thye Chua · Los Altos Hills, US
• Andrew K. Chan · San Jose, US
• John Birkner · Woodside, US
• Ralph G. Whitten · Reno, US
• Richard L. Bechtel · Sunnyvale, US
• Mammen Thomas · Seattle, US

Key dates

• Filing date: May 21, 1996
• Grant date: Jul 14, 1998
• Expiry date: May 21, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for forming a field programmable gate array with antifuses.