Programmable inverter circuit used in a programmable logic cell
US5781032A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Sep 9, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states. A first logic gate of the plurality of combinational logic circuits has first and second inputs each connected to a respective output node of one of two of the four inverter circuits, and a second logic gate has first and second inputs each connected to a respective output node of one of the other two of the four inverter circuits. The inverter circuits may be implemented as XNOR gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.