Test converage of embedded memories on semiconductor substrates
US5784323A · kind A · utility
32Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1997 |
| Grant date | Jul 21, 1998 |
| Priority date | — |
| Expiry date | Feb 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a device for testing memory having write cycles and read cycles. A BIST state machine changes the data applied to the memory's DI port during read cycles to a value different from that of the data stored in the currently addressed memory location. The BIST-generated expect data also is at a different value from that of data at the memory's DI port and at the same value as the data stored at the current memory address location during read operations. With this arrangement, flush through defects can be detected which would not have been detectable by prior BIST machines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.