Method for over-etching to improve voltage distribution
US5786240A · kind A · utility
11Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1996 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Jun 27, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/055
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An over-etched (OE) antifuse includes a lower electrode, an antifuse layer contacting the lower electrode by an over-etched via, and a second conductive layer formed on the antifuse layer. This over-etched via forms a trench in the lower electrode, wherein in one embodiment the depth of the trench approximates the thickness of the antifuse layer. The trench narrows the programming voltage distribution of the antifuses on the device, irrespective of topology. Because active circuits can be placed underneath the OE antifuses, the present invention dramatically reduces chip size in comparison to conventional devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.