Method of making a capacitor
US5786250A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1997 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Mar 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A method of the present invention forms a vertically oriented structure connected with a source/drain region through an open space. In one embodiment of the method wherein a capacitor storage node is formed, the open space is located between two word line gate stacks in a MOS DRAM memory circuit. A thin landing pad is formed of conducting material in the open space extending to the source/drain region and over the tops of the gate stacks. An insulating layer is formed over the gate stacks and the landing pad. A recess is etched down through the insulating layer to expose an annular portion of the landing pad. A volume of the insulating material is left upon the landing pad in the open space. A conductive layer is deposited in the recess making contact with the exposed annular portion of the landing pad. A dry etching process is used to remove a segment of the conductive layer formed over the volume of insulating material upon the landing pad, after which the volume of insulating material upon the landing pad is removed. Remaining is a storage node made upon of a continuous layer of conductive material that lines the recess and the open space. A dielectric layer and a cell plate are…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.