Method and system for implementing a cache coherency mechanism for utilization within a non-inclusive cache memory hierarchy
US5787478A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1997 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Mar 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system of implementing a cache coherency mechanism for supporting a non-inclusive cache memory hierarchy within a data processing system is disclosed. In accordance with the method and system of the invention, the memory hierarchy includes a primary cache memory, a secondary cache memory, and a main memory. The primary cache memory and the secondary cache memory are non-inclusive. Further, a first state bit and a second state bit are provided within the primary cache, in association with each cache line of the primary cache. As a preferred embodiment, the first state bit is set only if a corresponding cache line in the primary cache memory has been modified under a write-through mode, while the second state bit is set only if a corresponding cache line also exists in the secondary cache memory. As such, the cache coherency between the primary cache memory and the secondary cache memory can be maintained by utilizing the first state bit and the second state bit in the primary cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.