Method of making EEPROM cell device with polyspacer floating gate

US5789297A · kind A · utility

Assignee

• MOSEL VITELIC INC. · TW

Inventors

• Chih-Hsien Wang · Baoshan, TW
• Min-Liang Chen · Baoshan, TW
• Thomas Chang · Taichung, TW

Key dates

• Filing date: Oct 24, 1996
• Grant date: Aug 4, 1998
• Expiry date: Oct 24, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6892

Abstract

A novel electrically erasable programmable read only memory (EEPROM) cell for use in semiconductor memories includes a polyspacer floating gate. The EEPROM structure also includes a select gate covering a part of the channel of the EEPROM cell, with a polysilicon spacer adjacent to the select gate. The polysilicon spacer implements a floating gate that holds charge to program the EEPROM cell. In one embodiment, a isolation layer separates the select gate and the floating gate. The isolation layer and the floating gate extends over the remaining part of the channel. A second isolation layer is formed over select gate and the floating gate. A control gate is formed on the isolation layer. Between the drain and the control gate is the second isolation layer. A lightly doped drain (LDD) structure is formed at the drain adjacent.