Multiple bits-per-cell flash EEPROM memory cells with wide program and erase V.sub.t window
US5790456A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 1997 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | May 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided an improved method for performing channel hot-carrier programming in an array of multiple bits-per-cell Flash EEPROM memory cells in a NOR memory architecture so as to eliminate program disturb during a programming operation. The array has a plurality of memory cells arranged in rows of word lines and columns of bit lines intersecting the rows of word lines. A programming current source is connected to the source of selected memory cells that are to be programmed in the corresponding columns of bit lines. A programming gate voltage is applied to control gates of the selected memory cells, and a programming drain voltage is applied simultaneously to the common array ground line connected to the drains of all of the memory cells. Further, a relatively low voltage is applied simultaneously to all of the control gates of non-selected memory cells in the array which are not to be programmed during the programming operation so as to eliminate the program disturb.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.